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FUJITSU SEMICONDUCTOR DATA SHEET
DS04-21343-1E
ASSP
Single Serial Input PLL Frequency Synthesizer
On-Chip 2.5 GHz Prescaler
MB15E07
s DESCRIPTION
The Fujitsu MB15E07 is serial input Phase Locked Loop (PLL) frequency synthesizer with a 2.5 GHz prescaler. A 32/33 or a 64/65 can be selected for the prescaler that enables pulse swallow operation. The latest BiCMOS process technology is used, resuItantly a supply current is limited as low as 8 mA typ. This operates with a supply voltage of 3.0 V (typ.) Furthermore, a super charger circuit is included to get a fast tuning as well as low noise performance. As a result of this, MB15E07 is ideally suitable for digital mobile communications, such as GSM (Global System for Mobile Communications).
s FEATURES
* High frequency operation: 2.5 GHz max (@ P= 64/65) 1.8 GHz max (@P = 32/33) * Low power supply voltage: VCC = 2.7 to 3.6 V * Very Low power supply current : ICC = 8.0 mA typ. (VCC = 3 V) * Power saving function : IPS = 0.1 A typ. * Pulse swallow function: 32/33 or 64/65 * Serial input 14-bit programmable reference divider: R = 5 to 16,383 * Serial input 18-bit programmable divider consisting of: - Binary 7-bit swallow counter: 0 to 127 - Binary 11-bit programmable counter: 5 to 2,047 * Wide operating temperature: Ta = -40 to 85C * Plastic 16-pin SSOP package (FPT-16P-M05)
s PACKAGE
16-pin, Plastic SSOP
(FPT-16P-M05)
MB15E07
s PIN ASSIGNMENT
(Top View) R P LD/fout ZC PS LE Data Clock
OSCin OSCout Vp V CC Do GND Xfin fin
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
2
MB15E07
s PIN DESCRIPTIONS
Pin no. 1 Pin name OSCIN I/O I Descriptions Programmable reference divider input. Oscillator input. Connection for an crystal or a TCXO. TCXO should be connected with a coupling capacitor. Oscillator output. Connection for an external crystal. Power supply voltage input for the charge pump. Power supply voltage input. Charge pump output. Phase of the charge pump can be reversed by FC bit. Ground. Prescaler complementary input, and should be grounded via a capacitor. Prescaler input. Connection with an external VCO should be done with AC coupling. Clock input for the 19-bit shift register. Data is shifted into the shift register on the rising edge of the clock. (Open is prohibited.) Serial data input using binary code. The last bit of the data is a control bit. (Open is prohibited.) Control bit = "H" ;Data is transmitted to the programmable reference counter. Control bit = "L" ;Data is transmitted to the programmable counter. Load enable signal input (Open is prohibited.) When LE is high, the data in the shift register is transferred to a latch, according to the control bit in the serial data. Power saving mode control. This pin must be set at "L" at Power-ON. (Open is prohibited.) PS = "H" ; Normal mode PS = "L" ; Power saving mode Forced high-impedance control for the charge pump (with internal pull up resistor.) ZC = "H" ; Normal Do output. ZC = "L" ; Do becomes high impedance. Lock detect signal output(LD)/phase comparator monitoring output (fout). The output signal is selected by LDS bit in the serial data. LDS = "H" ; outputs fout (fr/fp monitoring output) LDS = "L" ; outputs LD ("H" at locking, "L" at unlocking.) Phase comparator output for an external charge pump. Nch open drain output. Phase comparator output for an external charge pump. CMOS output.
2 3 4 5 6 7 8 9
OSCOUT VP VCC DO GND Xfin fin Clock
O - - O - I I I
10
Data
I
11
LE
I
12
PS
I
13
ZC
I
14
LD/fout
O
15 16
P R
O O
3
MB15E07
s BLOCK DIAGRAM
OSCIN 1 fr Crystal Oscillator circuit OSCOUT 2 fp Programmable reference divider Binary 14-bit reference counter fr Intermittent mode control (power save) LE fp LE 11 1-bit control latch 19-bit shift register Data 10 C N T 19-bit shift register Charge pump 13 ZC 3 VP Super charger LE 18-bit latch 7-bit latch 11-bit latch 5 Do SW 17-bit latch 14-bit latch 3-bit latch LD Lock detector Phase comparator 16 R
15 P
PS 12
LDS FC LD/fr/fp selector
14 LD/fout
Clock 9
SW Programmable divider XfIN 7 fIN 8 64/65 GND 6 Control Circuit Prescaler 32/33, Binary 7-bit swallow counter Binary 11-bit programmable counter fp
V CC 4
MD
4
MB15E07
s ABSOLUTE MAXIMUM RATINGS
Parameter Power supply voltage Input voltage Output voltage Storage temperature Symbol VCC VP VI VO Tstg Rating -0.5 to +4.0 VCC to +6.0 -0.5 to VCC +0.5 -0.5 to VCC +0.5 -55 to +125 Unit V V V V C Remark
Note: Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
s RECOMMENDED OPERATING CONDITIONS
Parameter Power supply voltage Input voltage Operating temperature Symbol VCC VP VI Ta Value Min. 2.7 VCC GND -40 Typ. 3.0 - - - Max. 3.6 6.0 VCC +85 Unit V V V C Remark
Handling Precautions
* This device should be transported and stores in anti-static containers. * This is a static-sensitive device; take proper anti-ESD precautions. Ensure that personnel and equipment are properly grounded. Cover workbenches with grounded conductive mats. * Always turn the power supply off before inserting or removing the device from its socket. * Protect leads with a conductive sheet when handling or transporting PC boards with devices.
5
MB15E07
s ELECTRICAL CHARACTERISTICS
(VCC = 2.7 to 3.6 V, Ta = -40 to +85C) Value Unit Min. Typ. Max. - - 100 100 3 -10 500 Vcc x 0.7 - -1.0 -1.0 -1.0 Pull up input -100 0 -100 Open drain output - Vcc - 0.4 - Vp - 0.4 - - Open drain output - - 1.0 VCC = 3.0 V, Vp = 5 V, VDOH = 4.0 V, Ta = 25C VCC = 3.0 V, Vp = 5 V, VDOL = 1.0 V, Ta = 25C - 8.0 0.1 - - - - - - - - - - - - - - - - - - - - - - -10.0 - 10 1800 2500 40 +2 VCC - Vcc x 0.3 +1.0 +1.0 +1.0 0 +100 0 0.4 - 0.4 - 0.4 1.1 1.0 -1.0 - - mA - 10.0 - A mA mA V V mA A MHz MHz MHz dBm mVp-p
Parameter Power supply current*1 Power saving current Operating frequency Crystal oscillator operating frequency Input sensitivity fin OSCin Data, Clock, LE, PS, ZC Data, Clock, LE, PS Input current ZC OSCin P R, LD/fout
Symbol ICC Ips fin fOSC Vfin VOSC VIH VIL IIH IIL IIH IIL IIH IIL VOL VOH VOL VDOH VDOL
Condition fin = 1800 MHz, fosc = 12 MHz, P = 32/33 ZC = "H" or open P = 32/33 P = 64/65 min. 500 mVp-p 50 system (Refer to the test circuit.)
Input voltage
A A A V V
Output voltage
Do High impedance cutoff current
Do P R, LD/fout
IOFF IOL IOH IOL IDOH
Output current Do
IDOL
*1: Conditions; VCC = 3.0 V, Ta = 25C, in locking state. 6
MB15E07
s FUNCTION DESCRIPTIONS
Pulse Swallow Function
The divide ratio can be calculated using the following equation: fVCO = [(P x N) + A] x fOSC / R (A < N) fVCO : Output frequency of external voltage controlled oscillator (VCO) N : Preset divide ratio of binary 11-bit programmable counter (5 to 2,047) A : Preset divide ratio of binary 7-bit swallow counter (0 A 127) fOSC : Output frequency of the reference frequency oscillator R : Preset divide ratio of binary 14-bit programmable reference counter (5 to 16,383) P : Preset divide ratio of modules prescaler (32 or 64)
Serial Data Input
Serial data is processed using the Data, Clock, and LE pins. Serial data controls the programmable reference divider and the programmable divider separately. Binary serial data is entered through the Data pin. One bit of data is shifted into the shift register on the rising edge of the clock. When the load enable pin is high, stored data is latched according to the control bit data as follows:
Table.1 Control Bit
Control bit (CNT) H L Destination of serial data 17 bit latch (for the programmable reference divider) 18 bit latch (for the programmable divider)
Shift Register Configuration
Programmable Reference Counter
LSB Data Flow MSB
1 C N T
2 R 1
3 R 2
4 R 3
5 R 4
6 R 5
7 R 6
8 R 7
9 R 8
10 R 9
11 R 10
12 R 11
13 R 12
14 R 13
15 R 14
16
17
18
SW
FC
LDS
CNT : Control bit R1 to R14 : Divide ratio setting bit for the programmable reference counter (5 to 16,383) SW : Divide ratio setting bit for the prescaler (32/33 or 64/65) FC : Phase control bit for the phase comparator LDS : LD/fout signal select bit Note : Start data input with MSB first
[Table. 1] [Table. 2] [Table. 5] [Table. 7] [Table. 6]
7
MB15E07
Programmable Reference Counter
LSB Data Flow MSB
1 C N T
2 A 1
3 A 2
4 A 3
5 A 4
6 A 5
7 A 6
8 A 7
9 N 1
10 N 2
11 N 3
12 N 4
13 N 5
14 N 6
15 N 7
16 N 8
17 N 9
18 N 10
19 N 11
: Control bit CNT N1 to N11 : Divide ratio setting bits for the programmable counter (5 to 2,047) A1 to A7 : Divide ratio setting bits for the swallow counter (0 to 127) Note : Start data input with MSB first
[Table. 1] [Table. 2] [Table. 4]
Table2. Binary 14-bit Programmable Reference Counter Data Setting
Divide ratio (R) 5 6 * 16383 R 14 0 0 * 1 R 13 0 0 * 1 R 12 0 0 * 1 R 11 0 0 * 1 R 10 0 0 * 1 R 9 0 0 * 1 R 8 0 0 * 1 R 7 0 0 * 1 R 6 0 0 * 1 R 5 0 0 * 1 R 4 0 0 * 1 R 3 1 1 * 1 R 2 0 1 * 1 R 1 1 0 * 1
Note: * Divide ratio less than 5 is prohibited.
Table.3 Binary 11-bit Programmable Counter Data Setting
Divide ratio (N) 5 6 * 2047 N 11 0 0 * 1 N 10 0 0 * 1 N 9 0 0 * 1 N 8 0 0 * 1 N 7 0 0 * 1 N 6 0 0 * 1 N 5 0 0 * 1 N 4 0 0 * 1 N 3 1 1 * 1 N 2 0 1 * 1 N 1 1 0 * 1
Note: * Divide ratio less than 5 is prohibited. * Divide ratio (N) range = 5 to 2,047
8
MB15E07
Table.4 Binary 7-bit Swallow Counter Data Setting
Divide ratio (A) 0 1 * 127 A 7 0 0 * 1 A 6 0 0 * 1 A 5 0 0 * 1 A 4 0 0 * 1 A 3 0 0 * 1 A 2 0 0 * 1 A 1 0 1 * 1
Note: * Divide ratio (A) range = 0 to 127
Table. 5 Prescaler Data Setting
SW H L Prescaler Divide ratio 32/33 64/65
Table. 6 LD/fout Output Select Data Setting
LDS H L fout signal LD signal LD/fout output signal
Relation between the FC input and phase characteristics
The FC bit changes the phase characteristics of the phase comparator. Both the internal charge pump output level (DO) and the phase comparator output (R, P) are reversed according to the FC bit. Also, the monitor pin (fOUT) output is controlled by the FC bit. The relationship between the FC bit and each of DO, R, and P is shown below.
Table. 7 FC Bit Data Setting (LDS = "H")
FC = High Do fr > fp fr < fp fr = fp H L Z* R L H L P L Z* Z* LD/fout (fr) (fr) (fr) Do L H Z* H L L FC = Low R P Z* L Z* LD/fout (fp) (fp) (fp)
* : High impedance
9
MB15E07
When designing a synthesizer, the FC pin setting depends on the VCO and LPF characteristics.
: When the LPF and VCO characteristics are similar to , set FC bit high. : When the VCO characteristics are similar to , set FC bit low. VCO Output Frequency PLL LPF VCO
LPF Input Voltage
Power Saving Mode (Intermittent Mode Control Circuit)
Setting a PS pin to Low, the IC enters into power saving mode resultatly current sonsumption can be limited to 10A (max.). Setting PS pin to High, power saving mode is released so that the IC works normally. In addition, the intermittent operation control circuit is included which helps smooth start up from the power saving mode. In general, the power consumption can be saved by the intermittent operation that powering down or waking up the synthesizer. Such case, if the PLL is powered up uncontrolled, the resulting phase comparator output signal is unpredictable due to an undefined phase relation between reference frequency (fr) and comparison frequency (fp) and may in the worst case take longer time for lock up of the loop. To prevent this, the intermittent operation control circuit enforces a limited error signal output of the phase detector during power up, thus keeping the loop locked. During the power saving mode, the corresponding section except for indispensable circuit for the power saving function stops working, then current consumption is reduced to 10 A (max.). At that time, the Do and LD become the same state as when a loop is locking. That is, the Do becomes high impedance. A VCO control voltage is naturally kept at the locking voltage which defined by a LPF"s time constant. As a result of this, VCO's frequency is kept at the locking frequency. Note: * While the power saving mode is executed, ZC pin should be set at "H" or open. If ZC is set at "L" during power saving mode, approximately 10 A current flows. * PS pin must be set "L" at Power-ON. * The power saving mode can be released (PS : L H) 1s later after power supply remains stable. * During the power saving mode, it is possible to input the serial data.
Table.8 PS Pin Setting
PS pin H L Normal mode Power saving mode Status
Table.9 ZC Pin Setting
ZC pin H L Do output Normal output High impedance
10
MB15E07
s SERIAL DATA INPUT TIMING
Data
MSB
LSB
Clock
LE t2 t1 t7 On rising edge of the clock, one bit of the data is transferred into the shift register. t3 t4 t5 t6
Parameter
t1 t2 t3 t4
Min.
20 20 30 30
Typ.
- - - -
Max.
- - - -
Unit
ns ns ns ns
Parameter
t5 t6 t7
Min.
100 20 100
Typ.
- - -
Max.
- - -
Unit
ns ns ns
11
MB15E07
s PHASE COMPARATOR OUTPUT WAVEFORM
fr
fp tWU LD tWL
[ FC = "H" ]
P
R
H Do Z L
[ FC = "L" ]
P
R
H Do L Z
Notes: 1. Phase error detection range:-2to +2 2. Pulses on Do output signal during locked state are output to prevent dead zone. . 3. LD output becomes low when phase is tWU or more. LD output becomes high when phase error is tWL or less and continues to be so for three cysles or more. 4. tWU and tWL depend on OSCin input frequency. tWU 8/fosc (e g.tWU 625ns, foscin = 12.8 MHz) tWL 16/fosc (e g.tWL 1250ns, foscin = 12.8 MHz) 5. LD becomes high during the power saving mode (PS = "L".)
12
MB15E07
s TEST CIRCUIT (for Measuring Input Sensitivity fin/OSCin)
V CC V P 0.1F 1000pF P.G 50 1000pF 8 9 7 6 0.1F 50 5 4 3 2 1 1000pF P.G
10 11 12 13 14 15 16 Oscilloscope
Controller (setting devide ratio)
V CC
13
MB15E07
s APPLICATION EXAMPLE
Output LPF 10k 12k To a lock detect. 12k 10k VCO
From
R 16 15
P
LD/F OUT 14 13
ZC
PS 12 11
LE
Data 10 9
Clock
MB15E07
1 OSC IN
2 OSC OUT
3 VP
4 V CC
5 DO
6 GND
7 Xf IN 1000pF
8 f IN 1000pF
X' tal C1 C2 0.1 F 0.1 F
C 1, C 2 : Depend on the crystal parameters
(Continued)
14
MB15E07
s TYPICAL CHARACTERISTICS
Do Output Current
[Ta = + 25C] [V CC = 3 V, Vp = 3 V, 5 V] 5.0 4.0 Vp = 3 V Vp = 5 V 5.0 4.0 [Ta = + 25C] [V CC = 3 V, Vp = 3 V, 5 V] Vp = 3 V Vp = 5 V
V OH (V)
3.0 2.0 1.0 0 0 -5 -10 I OH (mA) -15 -20
V OL (V)
3.0 2.0 1.0 0 0 5 10 I OL (mA) 15 20
fin Input Sensitivity
Vfin vs. fin [Ta = +25C] +10 0
Prescalar = 64/65 Main. counter div. ratio = 4104 Swallow = "ON" V CC = Vp
Vfin (dBm)
SPEC
-10 -20 V CC = 2.7 V -30 -40 0 1000 2000 fin (MHz) 3000 4000 V CC = 3.0 V V CC = 3.6 V
(Continued)
15
MB15E07
(Continued)
fin Input Snsitivity
[Ta = 25C] +10
Prescaler = 32/33 Main, counter div. ratio = 1860 Swallow = "ON"
0
SPEC
Vfin (dBm) -10
-20
: VDD = 2.7 V : VDD = 3.0 V : VDD = 3.6 V
-30
-40 0 1000 fin (MHz) 2000 3000
OSCin Input Characteristics
Vf OSC vs. f OSC [Ta = +25C] +10 Ref. counter div. ratio = 767 fin, Xfin : OPEN
SPEC
0 -10 -20 -30 -40 0 50 100 f OSC (MHz) 150 V CC = 2.7 V V CC = 3.0 V V CC = 3.6 V 200
Vf OSC (dBm)
(Continued)
16
MB15E07
(Continued)
fin Input Impedance
fin
4 : 39.314 - 50.516 k 3.2159 pF 2 500.000 000 MHz 1 : 10.188 - 36.666 1 GHz 4 2 : 10.371 1.4438 3 1.5 GHz 3 : 16.474 31.454 2 GHz 2
1
OSCin Input Impedance
3 : 030.13 -2.389 k 3.331 pF 20.000 000 MHz 1 : 3.516 - 43.99 k 1 MHz 2 : 150.5 - 4.8388 k 10 MHz 4 : 12.844 - 948.37 50 MHz
OSCin
3 1 2 4
17
MB15E07
s REFERENCE INFORMATION
Test Circuit Diagram (PCN Application)
3.65 V
Data interface board & PC
3.65 V R 16 P 15 LD fout 14 ZC 13 PS 12 LE 11 Data 10 9 47 k 47 k 47 k MB15E07 Clock
-Comparison freq ; 200 kHz -R div ratio ; 65 -Prescaler Div ; 64/65 -foL = 1604 MHz -foM = 1642 MHz -foH = 1679 MHz
1 OSCin f OSC = 13 MHz
2 OSCout
3 Vp
4 V CC
5 DO
6 GND 33 pF
7 xfin 1 nF
8 fin -Spectrum Analyzer -Time Interval Analyzer cox. 18
NC GND P Kv = 43 MHz/V (MQE523-1619) C GND B
Signal Generator HP8642B
100 pF 51 cox. +
0.1
0.1
18 18
Output
Vsupply = 3.65 V
10 + 10 1n
27 k 1k 33 n (film cap) 120 p
V VCO = 3.65 V + cox. 0.1 10
(Continued)
18
MB15E07
(Continued)
PLL Lock Up toem = 420 s (1604 MHz1679 MHz, within = 1kHz)
Mkr x : 420.01163 s y : -74.9991 MHz 30.00500 MHz
PLL Phase Noise @within loop band = -77.5 dBc/Hz
MKR REF -7.7 dBm 10 dB/ ATT 00 dB 13.02 kHz -52.7 dB
2.00 kHz/div
RBW 300 kHz VBW 300 kHz
29.99500 KHz 5.1372 s 1.9953872 s
SPAN 60.0 MHz
CENTER 1.6420000 GHz
PLL Lock Up toem = 400 s (1679 MHz1604 MHz, within 1 kHz)
Mkr x : 400.01227 s y : -75.0020 MHz 30.00500 MHz
PLL Reference Leakage 200 MHz offset = -70.0 dBc
MKR -200 kHz -70 dB
REF -7.2 dBm 10 dB/
ATT 00 dB
2.00 kHz/div
RBW 10 kHz VBW 10 kHz
29.99500 KHz 5.1366 s 1.9953866 s SPAN 1.00 MHz CENTER 1.67900 GHz
19
MB15E07
s ORDERING INFORMATION
Part number MB15E07PFV1 Package 16-pin Plastic SSOP (FPT-16P-M05) Remarks
20
MB15E07
s PACKAGE DIMENSION
16 pins, Plastic SSOP (FPT-16P-M05)
* 5.000.10(.197.004)
* : These dimensions do not include resin protrusion.
1.25 -0.10 +.008 .049 -.004
+0.20
0.10(.004)
INDEX
*4.400.10
(.173.004)
6.400.20 (.252.008)
5.40(.213) NOM
0.650.12 (.0256.0047)
0.22 -0.05 +.004 .009 -.002
+0.10
"A"
0.15 -0.02 +.002 .006 -.001
+0.05
Details of "A" part 0.100.10(.004.004) (STAND OFF)
4.55(.179)REF
0
10
0.500.20 (.020.008)
C
1994 FUJITSU LIMITED F16013S-2C-4
Dimensions in mm (inches)
21
FUJITSU LIMITED
For further information please contact:
Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT, 4-1-1, Kamikodanaka Nakahara-ku, Kawasaki-shi Kanagawa 211-88, Japan Tel: (044) 754-3763 Fax: (044) 754-3329 North and South America FUJITSU MICROELECTRONICS, INC. Semiconductor Division 3545 North First Street San Jose, CA 95134-1804, U.S.A. Tel: (408) 922-9000 Fax: (408) 432-9044/9045 Europe FUJITSU MIKROELEKTRONIK GmbH Am Siebenstein 6-10 63303 Dreieich-Buchschlag Germany Tel: (06103) 690-0 Fax: (06103) 690-122 Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE. LIMITED #05-08, 151 Lorong Chuan New Tech Park Singapore 556741 Tel: (65) 281-0770 Fax: (65) 281-0220
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. FUJITSU semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with FUJITSU sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Control Law of Japan, the prior authorization by Japanese government should be required for export of those products from Japan.
F9703 (c) FUJITSU LIMITED Printed in Japan
24

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